CAN on FPGA

• Conforms to CAN 2.0B standard.
• Supports both standard (11 bit frame identifier) and extended frame (29 bit idientifier). Possible to mix frame types without reconfiguration of the interface.
• Supports standard CAN bit rate up to 1Mbps with 40 MHz CAN clock. Other/higher rates possible.
• Asynchronous/independent OPB bus clock and CAN clock.
• Receive FIFO with 64 bytes.
• Dynamic utilized, i.e. number of frames depends on frame size.
• Using distributed RAM, i.e. no Block RAM.
• Automatic retransmission.
• Receive and transmit error counter.
• OPB bus interface. Easy to integrate in PowerPC or MicroBlaze based design.
• Example application and drivers available.
• Easy to adapt to other bus interfaces, e.g. asynchronous bus.
• Xilinx devices families: All Spartan 3 families and all Virtex families.
• Easy to port to other FPGA/ASIC devices.
• License not locked to any FPGA vendor etc, i.e. high FPGA device souring freedom.

FPGA resources used – Xilinx Spartan 3.